(1) Field of the Invention
The invention relates generally to electronic circuit design. More particularly, the present invention relates to the adjustment of sample rates by measuring sample rates of incoming digital bit streams in digital to analog converters.
(2) Description of the Prior Art
Sound is an analog quantity and it has historically been recorded, stored, transmitted and replayed in an analogue way. Obviously, the advent of digital technology has had a huge impact on the audio industry and more of the audio engineering requirements are being realized using digital techniques. It is therefore necessary to be able to convert audio signals between the analog and digital domains.
The block diagram of FIG. 1 prior art illustrates the principal building blocks of a prior art basic digital to analog converter. Normally a bitstream 1 (from CD, tape or transmission) is taken and converted in a digital to analog converter 2 back to an analog signal 3. This is a multi-stage process.
Clock signal input 4 shown in FIG. 1 prior art is used and is associated with the incoming digital data stream so that the digital to analog conversion process is operating at the correct sample rate. The incoming data stream will have some jitter on it, so it is important to eliminate this. A phase locked loop circuit is usually used, which has the effect of maintaining a constant clock at the output, based on the average incoming clock frequency, damping out variations sitter).
In block 5, an input format converter, the arriving digital bit stream must be split up into words, so that the correct bits are combined to make up the correct word. There are many methods of packaging the bits, called framing, to allow additional features like error correction and other non-audio data to be incorporated in the data stream. Obviously, this data must be removed from the audio stream before conversion.
In block 6, a digital to analog block, the digital word is then converted to an analogue sample, using the reverse process to quantization. A digital to analogue converter produces an analog voltage at each sample time. There are a variety of techniques used to achieve this.
There are various patents to describe various embodiments of digital to analog converters:
U.S. patent (U.S. Pat. No. 6,531,975 to Trotter et al.) describes an apparatus and method for converting digital input signals sampled at different rates to analog signals including a digital to analog converter for each digital input signal. Each digital to analog converter receives a digital input signal and a clock signal corresponding to the sampling rate of the received digital input signal. The apparatus can also receive a set of sample rate signals indicating the sampling rate for each digital input signal. The sample rate signals are used to route each digital input signal, along with a corresponding clock signal, to a corresponding digital to analog converter (DAC). A clock error signal controls routing of the digital input signals to the DACs as well as operation of the DACs. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.
U.S. patent (U.S. Pat. No. 6,201,486 to Chan et al.) discloses how for a system having multiple sources of digital input data to be converted to analog by Digital to Analog Converters (DACs), pre-processing of the multiple sources of data is provided, such that differences in input sampling rates are accommodated. When multiple digital input sources are to be converted to analog signals in a single integrated circuit, these input signals are routed to a clock generator having Phase Locked Loop (PLL) circuitry and to respective Asynchronous Sample Rate Converters (ASRCs). Sample rate information relating to an input signal selected from among the multiple input signals is determined during a locking operation of the PLL. Based on the common clock output from the clock generator, the ASRCs convert the input signals to a single sampling rate. Once the multiple input sources are converted to a common sample rate by the ASRCs, the inputs are converted to analog signals by DACs using the common clock and are output by the single Integrated Circuit.
U.S. patent (U.S. Pat. No. 5,600,320 to Wilson et al.) describes a method and apparatus for digital-to-analog conversion using sigma-delta modulation of the temporal spacing between digital samples are provided. The method and apparatus include sigma-delta modulation of the time-base such that errors produced by non-uniform sampling are frequency-shaped to a high frequency region where they are reduced by conventional filtering techniques. In one embodiment, an oversampling modulator receives digital input samples and, responsive to a noise-shaped clock signal, modulates the digital input samples to produce modulated samples at an oversampling rate. The oversampling rate preferably is equal to an oversampling ratio times a preselected input sample rate. A DAC, coupled to the modulator, converts the modulated samples to an analog signal. A modulator sample rate control circuit, coupled to the modulator, receives a frequency select signal representing the preselected input sample rate, and produces the noise-shaped clock signal for controlling operation of the modulator at the oversampling rate. The control circuit preferably includes a first sigma-delta modulator that sigma-delta modulates the frequency select signal. The oversampling modulator preferably includes a second sigma-delta modulator.